Design of 25 Gbit/s half-rate CDR with 1:2 demultiplexer for

发布时间：2024-03-24 00:43

　　A 25 Gbit/s clock and data recovery(CDR) circuit with 1:2 demultiplexer for 100 Gbit/s Ethernet(100 Gb E) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company(TSMC) 65 nm complementary metal-oxide-semiconductor(CMOS) technology. A novel quadrature voltage-controlled-oscillator(QVCO) structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array ...

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